1. Field of the Invention
This invention relates to a semiconductor memory device such as an EEPROM or EPROM which is constructed by a semiconductor integrated circuit, and more particularly to a semiconductor memory device having monitoring function for measuring the threshold levels of a large number of memory cells includes a memory cell array.
2. Description of the Related Art
In a nonvolatile semiconductor memory which is formed in an LSI configuration like an EEPROM constructed by an array of electrically erasable and programmable read only memory cells or an EPROM constructed by an array of ultra violet erasable and programmable read only memory cells, a monitoring circuit for externally determining the states of the memory cells, for example, the threshold levels of the memory cells, is provided.
FIG. 9 shows an example of a monitoring circuit contained in the conventional EEPROM, and the monitoring circuit is formed in the integrated circuit chip in position different from the memory cell array. The monitoring circuit includes an EEPROM cell 71 having the same construction as the memory cell constituting the memory cell array formed in the semiconductor chip. The EEPROM cell 71 is provided by a series circuit of a floating gate MOS transistor 72 for a memory cell and a cell selects MOS transistor 73. The drain and gate electrodes of the MOS transistor 72 and the gate and source electrodes of the MOS transistor 73 are connected to monitoring pads 74, 75, 76 and 77 provided on the semiconductor chip.
When the monitoring circuit of the above construction is used to monitor the EEPROM, detecting needles or the like are in contact with the respective pads 74 to 77 from the exterior of the chip to determine the operating condition of the monitoring EEPROM cell 71. However, the EEPROM having the monitoring circuit contained therein has the following defects.
First, since it is necessary to set the detecting needles in contact with the pads 74 to 77 provided on the integrated circuit chip when monitoring the EEPROM, the monitoring operation cannot be effected after the integrated circuit chip is molded with resin and the EEPROM cannot be evaluated after it is provided as a finished product.
Secondly, since it is necessary to form a plurality of pads each of which requires a relatively large occupied area on the semiconductor chip, the finite chip area cannot be effectively used.
Thirdly, the monitoring circuit is formed in position different from the memory cell array and it monitors a memory cell different from a memory cell which is actually operated. That is, the memory cells include the memory cell array cannot be directly monitored and each of the memory cells cannot be checked and evaluated at the LSI level on the entire memory cell array.